(1) Fields of the Invention
The present invention relates generally to fabrication of semiconductor devices and more particularly to a structure and a process which results in a field effect transistor (FET) semiconductor device salicided T shaped or alternatively, a Y shaped gate structure with reduced parasitic resistance and capacitance, and improved high speed performance.
(2) Description of Prior Art
As field effect transistor (FET) devices are scaled down to have channel lengths in the submicron and deep submicron ranges as required for the device densities of ultra large scale integration (ULSI), gate electrical characteristics can be degraded. This is particularly true for ultra high speed devices such as RF devices, whereby the increase in sheet resistance of the gate electrode structure with decreasing gate structure size, can degrade device high speed performance. Salilicided structures have been proposed for these ultra small gate elements, but the narrow line width effect causes an increase in the effective sheet resistance of the gate contact element, with salicide agglomeration a contributing factor, as well as creating difficulties with the fabrication process as the technology is scaled down to submicron and deep submicron regions.
When an ultra high speed integrated circuit is designed and fabricated, several high frequency characteristics are important. Gate structure sheet resistance is a contributing factor to cutoff frequency (f.sub.t), gate parasitic resistance, gate delay time (charging constant), and maximum frequency performance. (f.sub.max). In general, as channel length and subsequently gate length is decreased, high speed and high frequency performance is improved. However, the reduction of the gate length for devices in the submicron range causes a salicide agglomeration which usually increases the effective gate conductor sheet resistance, and hence degrades high speed performance characteristics. A T or Y shaped gate structure has the advantage of maintaining or increasing the area of the gate conductor without increasing the essential channel length. The increased area of a salicided T or Y gate structure will improve the effective sheet resistance of the gate electrode structure over a conventional gate structure, and may even reduce the effective resistance with decreasing gate length for certain salicides such as Co salicide. (See "A Novel Self-Aligned T-Shaped Gate Process for Deep Submicron Si FET Fabrication authored by Horng-Chih Lin et al., IEEE Electron Device Letters, Vol. 19, NO. 1 January 1998, pages 26 through 28.)
Metal T shaped gate electrode structures have been utilized in the art, but the manufacturing processes can be expensive, unduly complex, and not as compatible with Si ULSI processes as desired.
U.S. Pat. No. 5,053,849 issued to Izwa et al. shows an overlapping gate/drain two layer gate structure, U.S. Pat. No. 5,817,558 issued to Wu describing a T-shaped gate formed of amorphous silicon, U.S. Pat. No. 5,559,049 issued to Cho shows a T-gate structure with a single poly layer and capacitively coupled auxiliary side gates, U.S. Pat. No. 5,856,232 describes a T-gate made of contact metal, as does U.S. Pat. No. 5,288,660 issued to Hua et al.
The following technical reports discuss high performance gate structures.
A Novel Self-Aligned T shaped Gate Process for Deep Submicron Si MOSFET's Fabrication, author(s) Lin et al. IEEE Electron Device Letters, Vol. 19, No. 1, January 1998, pp26 to 28. Sub 100NM Gate length Metal Gate NMOS transistors fabricated by a replacement gate Process by Chatterjee et al., journal not identified.
A High Performance 0.1 um CMOS with Elevated Silicide using Novel Si SEG Process by Wakabayahi et al., journal not identified.
A Low Resistance Self Aligned T-Shaped Gate for High Performance Sub 0.1 Um CMOS by Hisamoto et al., IEEE transactions on Electron Devices, Vol. 44 No. 6, June 1997, pp. 951-956.